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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
www.ti.com
5.15.2 LCDC Electrical Data/Timing
Table 5-41. Timing Requirements for LCD LIDD Mode (1) (see Figure 5-31 through Figure 5-38 )
NO.
CV DD = 1.05 V
MIN MAX
MIN
CV DD = 1.3 V
MAX
UNIT
16
17
t su(LCD_D-CLK)
t h(CLK-LCD_D)
Setup time, LCD_D[15:0] valid
before LCD_CLK rising edge
Hold time, LCD_D[15:0] valid after
LCD_CLK rising edge
27
0
42
0
ns
ns
(1)
Over operating free-air temperature range (unless otherwise noted)
Table 5-42. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode (see
Figure 5-31 through Figure 5-38 )
NO.
PARAMETER
CV DD = 1.05 V
MIN MAX
MIN
CV DD = 1.3 V
MAX
UNIT
4
5
6
7
8
9
10
11
12
13
14
15
t d(LCD_D_V)
t d(LCD_D_I)
t d(LCD_E_A)
t d(LCD_E_I)
t d(LCD_A_A)
t d(LCD_A_I)
t d(LCD_W_A)
t d(LCD_W_I)
t d(LCD_STRB_A)
t d(LCD_STRB_I)
t d(LCD_D_Z)
t d(Z_LCD_D)
Delay time, LCD_CLK rising edge
to LCD_D[15:0] valid (write)
Delay time, LCD_CLK rising edge
to LCD_D[15:0] invalid (write)
Delay time, LCD_CLK rising edge
to LCD_CSx_Ex low
Delay time, LCD_CLKrising edge
to LCD_CSx_Ex high
Delay time, LCD_CLKrising edge
to LCD_RS low
Delay time, LCD_CLK rising edge
to LCD_RS high
Delay time, LCD_CLK rising edge
to LCD_RW_WRB low
Delay time, LCD_CLK rising edge
to LCD_RW_WRB high
Delay time, LCD_CLK rising edge
to LCD_EN_RDB high
Delay time, LCD_CLK rising edge
to LCD_EN_RDB low
Delay time, LCD_CLK rising edge
to LCD_D[15:0] in 3-state
Delay time, LCD_CLK rising edge
to LCD_D[15:0] valid from 3-state
-6
-6
-6
-6
-6
-6
5
5
5
5
5
5
-6
-6
-6
-6
-6
-6
7
7
7
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
126
Peripheral Information and Electrical Specifications
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